1. Field of the Invention
The present invention relates to a communication control apparatus performing data communication control.
2. Description of Related Art
Before an explanation on a conventional art, at first explanation will be made on a general connecting state of nodes with respect to a common line in a communication system and on a waveform pattern used in general data communication, referring to FIG. 1 and FIG. 2.
FIG. 1 is a schematic diagram showing a configuration example of a general communication system in which a plurality of nodes are connected to a common data line. In FIG. 1, reference characters 1a, 1b and 1c respectively designate a first node, second node and third node. Each of the nodes 1a, 1b, and 1c is composed of a communication control apparatus having communication control function and a microcomputer, not shown however. Each of the nodes 1a, 1b and 1c is connected to the common data line 4 respectively through transmitting buffer 2a, 2b and 2c, and through receiving buffer 3a, 3b and 3c.
In such a configuration of a communication system as shown in FIG. 1, in the case, for example, where the first node 1a transmits data to the third node 1c, the first node 1a delivers data to the common data line 4 through the transmitting buffer 2a. The data delivered from the first node 1a to the common data line 4 is inputted to the third node 1c and, at the same time, is inputted again to the first node 1a from which the data has been delivered, and further, in this case, is inputted also to the irrelevant second node 1b through the receiving buffer 3b. In addition, such a method that a node itself which has delivered data receives the data again is called echo back and the data received again is called echo back data.
By the way, in the data to be delivered to the common data line 4, data showing an object node of transmission, that is, a node which should receive the data (in this case, the third node 1c) is included. According to the data showing the object node of transmission, the second node 1b judges that it is not the data transmitted to itself and does not perform receiving operation, and the third node 1c judges that it is the data transmitted to itself and performs receiving operation.
And in case of the communication system shown in FIG. 1, CSMA/CD (Carrier Sense Multiple Access/Collision Detection) method is used as a bus competition control method. As for a bus occupation right of the common data line 4 in the case, for example, where the first node 1a and the second node 1b start transmitting at the same time, a node of high priority can occupy a bus by comparing echo back data with data transmitted from the node itself (in the following, to be called echo back comparison).
Next, explanation will be made on bit pattern of data communication used both in prior art and in the present invention, referring to FIG. 2.
FIG. 2 is a waveform diagram showing an example of bit pattern having been performed Pulse Width Modulation (in the following, to be called PWM), and the waveform transmitted to the common data line 4 shown in the aforesaid FIG. 1 is stipulated by the bit pattern explained in the following.
In FIG. 2, one bit region of data is composed of three divided areas (in the following, each of them called a time). As shown in FIG. 2 (a), bit "1" is represented by a first time being "H" (high level) and by a second and a third times both being "L" (low level). And as shown in FIG. 2 (b), bit "0" is represented by the first time and second time both being "H" and by the third time being "L". Transmit data configures each bit of communication data according to such bit pattern as "1" or "0" and to the positions before and behind it, a mark SOM (Start of Message) meaning transmission starting as shown in FIG. 2 (c), a mark EOM (End of Message) meaning transmission ending as shown in FIG. 2 (d) and a mark IMS (Inter Message Separation) meaning allowing the next transmission as shown in FIG. 2 (e) are added.
In addition, SOM has a pattern in which all of the first through the fourth times have "H" and both the fifth and sixth times have "L", being composed of six times of the sum, EOM has a pattern in which all of the first through the six times have "L", being composed of six times of the sum, and IMS has a pattern in which all of the first through the third have "L", being composed of three times of the sum.
Next, explanation will be made on the configuration of the conventional example of the communication control apparatus, referring to FIG. 3.
FIG. 3 is a block diagram showing essential parts of the conventional communication apparatus, that is, parts where transmitting and receiving are performed, and, more specifically, is a block diagram showing parts conducting interfacing with respect to the common data line 4.
As shown in the block diagram of FIG. 3, the essential parts of the conventional communication control apparatus 1 is composed of a transmitting unit designated by reference numeral 17, a receiving unit designated by 18, and, as the others, a sequence control unit 19, a line state detecting unit 29, an echo back comparison detecting unit 30, an echo back comparing resister 30 and the like.
The transmitting unit 17 is composed of a transmitting buffer memory 20, a P to S (Parallel to Serial) shift register 21, a PWM unit 22, a transmission mark generating unit 23, a selector 24, a transmitting buffer 2 and the like. In the transmitting buffer memory 20, data to be transmitted is stored. The data train stored in this transmitting buffer memory 20 as parallel data is converted into serial data by the P to S shift register 21. The serial data converted by the P to S shift register 21 is pulse-width modulated by the PWM unit 22. The transmission mark generating unit 23 generates SOM aforementioned. Either of the SOM pattern generated by this transmission mark generating unit 23 or the bit pattern modulated by the PWM unit 22 is selected by the selector 24 and outputted from the transmitting buffer 2 to the common data line 4.
And the receiving unit 18 is composed of a receiving buffer 3, a digital filter 25, a PWDM (Pulse Width Demodulation) unit 26, an S to P (Serial to Parallel) shift register 27, a receiving buffer memory 28 and the like. The communication data at the common data line 4 is removed of noise component by a digital filter 25 connected through the receiving buffer 3, and is pulse-width demodulated by the PWDM unit 26. Since the data having been pulse-width demodulated by the PWDM unit 26 is serial data, it is converted into parallel data by the S to P shift register 27 and is written into the receiving buffer memory 28.
And at the outside of the transmitting unit 17 and the receiving unit 18, a sequence control unit 19, a line state detecting unit 29 connected with the output of the digital filter 25 so as to observe a state of receive data, an echo back comparing register 30 and an echo back comparison detecting unit 61 which are used for echo back comparison, are provided. A comparison output of the echo back comparison detecting unit 30 and a detection data output of the line state detecting unit 29 are inputted in the sequence control unit 19.
Next, explanation will be made on the operation of the communication control apparatus of the conventional example whose configuration is shown in FIG. 3 aforementioned, referring to FIG. 3, FIG. 4 and FIG. 5.
FIG. 4 and FIG. 5 are timing charts explanatory of operations of the transmitting unit 17, receiving unit 18 and the echo back comparison detecting unit 30 and sequence control unit 19.
At first, at the time when data to be transmitted is written in the transmitting buffer memory 20, a transmitting buffer full signal 32 shown in FIG. 4 (a) rises to become "H" level so as to be inputted to the sequence control unit 19. And in the case where the state of the common data line 4 detected by the line state detecting unit 29 is coincided with IMS shown in FIG. 2 (e) aforementioned, a transmission allowing flag 33 is generated as shown in FIG. 4 (b) so as to be inputted in the sequence control unit 19. The sequence control unit 19 generates a transmission start flag 34 showing transmission starting shown in FIG. 4 (c) corresponding to the fact that the transmitting buffer full signal 32 aforementioned is inputted therein and to the transmission allowing flag 33. According to the generation of the transmission start flag 34, all of the configuration elements of the transmitting unit 17 are actuated.
A transmission start mark (SOM), depicted in FIG. 4 (d) and generated by the transmission mark generating unit, is provided to one input of the selector 24 and one byte of a transmission data train 40, selected by an address 36 provided to the to the transmitting buffer memory and transferred to the P to S shift register 25 in response to P to S load signal 24, is provided to other input of the selector 24. At this time, since the selector 24 selects the SOM 35 outputted from the transmission mark generating unit 23 by a selector control signal 38 given from the sequence control unit 19 shown in FIG. 4 (j), the SOM 35 is delivered to the common data line 4 through the transmitting buffer 2. After the SOM 35 is delivered to the common data line 4, the selector 24 selects an output (PWM output) 42 of the PWM unit 22 shown in FIG. 4 (i) by the selector control signal 38. At this time point, a P to S shift clock 39 shown in FIG. 4 (f) is inputted in the P to S shift register 21. The P to S shift register 21 performs shift operation with the rising to "H" level of the P to S shift clock 39 as trigger, and the highest output bit data (7) in the transmission data train of one byte which has been taken in is outputted at the timing shown in FIG. 4 (g).
In the following, the P to S shift register 21 outputs output bit data being from the second output bit data (6) to the lowest output bit data (0) of one-byte transmission data train 40 successively as serial data. Since the P to S shift clock 39 is inputted in the same way also in the echo back comparing register 31, an echo back comparing register output 41 is generated at the timing shown in FIG. 4 (h).
On the other hand, the serial output data bit of the P to S shift register 21 inputted to the PWM unit 22 is pulse-width modulated successively by the PWM unit 22 so as to be outputted as the PWM output 42 as shown in FIG. 4 (i) to the selector 24. At this time, as aforementioned, since the selector 24 selects the PWM output 42, the PWM output 42, as a selector output 43 shown in FIG. 5 (k), is delivered to the common data line 4 through the transmitting buffer 2, a waveform 44 at the common data line 4 is to be the one as shown in FIG. 5 (l).
Next, explanation will be made on the operation of the receiving unit 18. The waveform at the common data line 4 is transmitted to the digital filter 25 through the receiving buffer 3. The digital filter 25 outputs a digital filter output 46 as shown in FIG. 5 (n) obtained by a filtering process modulated serial data on the basis of a digital filtering sampling clock 45 shown in FIG. 5 (m), so as to input it in the PWDM unit 26. At this time, as shown in FIG. 5 (n), since time t1 is required for filtering process, a digital filter output 46 is delayed by time t1, with respect to the waveform 44 at the common data line 4.
And the PWDM unit 26 outputs a PWDM output 48 shown in FIG. 5 (p) to the S to P shift register 27 as demodulated serial data obtained by pulse-width demodulating the digital filter output 46, on the basis of "H" level pulse of a PWDM sampling clock 47 shown in FIG. 5 (o). Time t2 required for demodulating process shown in FIG. 5 (p) is to be delay time of output timing of the PWDM output 48 which is demodulated serial data with respect to output timing of the digital filter output 46.
Next, by the fact that the S to P shift register 27 is given a shift clock 49 shown in FIG. 5 (s), data which has been pulse-width demodulated is taken in the S to P shift register 27 successively. At the time when eight-bit data is taken in the S to P shift register 27, a pulse 50 which opens a receiving buffer writing gate (not shown in FIG. 3) is given, and parallel data for one byte is written in the receiving buffer memory 28 corresponding to a receiving buffer address 51. In the following, according to the same operation, receive data train is stored successively in the receiving buffer memory 28.
On the other hand, in the echo back comparison detecting unit 30, as shown in FIG. 4 (h), the echo back comparing resister output 41 and the PWDM output 48 are compared with each other on the basis of an echo back comparing clock 52 shown in FIG. 5 (q). As a result to this comparison, a logical "H" signal is output from the echo back comparison detecting unit 30 when the output of the echo back comparing register 30 and PWDM Unit are the same and a logical "L" is output when they are not the same. The sequence control unit 19 which has received the echo back comparison detecting data 53 outputs a transmission stop signal 54 shown in FIG. 5 (t) having a meaning of stopping transmission, in the case where it receives "H" signal. At the time when this transmission stop signal 54 is outputted from the sequence control unit 19, a reset signal not shown is inputted in the transmitting unit 17 and transmission operation is finished.
In the conventional communication control apparatus having such an echo back comparing function as aforementioned, echo back accuracy is dependent upon the delay time t1, of the digital filter 25 until serial data transmitted from the transmitting unit 17 is received by the receiving unit 18 or on the delay time t2 required for demodulating pulse width by the PWDM unit 26. That is to say, there has been a problem that a tolerance of delay is reduced at a load resistance or load capacity connected to the common data line 4.
And since the essence of echo back comparing is to judge whether or not receive data is coincided with the transmit data of "itself", abnormality can't be detected so long as transmit data is coincided with receive data even in the case where output data has something abnormal according to an accident of the transmitting unit 17 of itself, and transmission is continued as it is. Therefore, abnormal waveforms are continuously delivered to the common data line 4, resulting in giving bad effect to the whole transmission system or the like.